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2.1 RF Port
The receiver and the transmitter share the same RF pins. Figure 3 shows the implementation of the common
front-end. In transmit mode, the PA and the PA regulator are on; the voltage on VDD_PA pin is the nominal volt-
age of the regulator, about 1.8 V. The external inductances L1 and L4 are used for the PA. In receive mode, both
PA and PA regulator are off, and VDD_PA is tied to ground. The external inductances L1 and L4 are used for bi-
asing and matching the LNA, which is implemented as a common gate amplifier.
In te r n a l R F P o r t D e ta il
V D D _ P A
R X O N
V R E G
L 1
L 4
A n te n n a
S A W
F ilte r
+
+
P o w e r
A m p
L N A
D r iv e r
R e c e iv e r
Figure 3
2.2 Transmitter
The TRC103 is set to transmit mode when MCFG00_Chip_Mode[7..5] bits are set to 100. In continuous mode
the transmitted data is sent directly to the modulator. The host microcontroller is provided with a bit rate clock by
the TRC103 to clock the data; using this clock to send the data synchronously is mandatory in FSK configuration
and optional in OOK configuration. In buffered mode the data is first written into the 64-byte FIFO via the SPI in-
terface; data from the FIFO is then sent to the modulator.
At the front end of the transmitter, I and Q signals are generated by the base-band circuit which contains a digital
waveform generator, two D/A converters and two anti-aliasing low-pass filters. The I and Q signals are two quad-
rature sinusoids whose frequency is the selected frequency deviation. In FSK mode, the phase shift between I
and Q is switched between +90° and -90° according to the input data. The modulation is then performed at this
stage, since the information contained in the phase shift will be converted into a frequency shift when the I and Q
signals are combined in the first mixers. In OOK mode, the phase shift is kept constant whatever the data. The
combination of the I and Q signals in the first mixers creates a fixed frequency signal at a low intermediate fre-
quency which is equal to the selected frequency deviation. After D/A conversion, both I and Q signals are filtered
by anti-aliasing filters whose bandwidth is programmed with the register TXCFG1A_TXInterpfilt[7..4] . Behind the
filters, a set of four mixers combines the I and Q signals and converts them into two I and Q signals at the second
intermediate frequency which is equal to 1/8 of the LO frequency, which in turn is equal to 8/9 of the RF frequen-
cy. These two new I and Q signals are then combined and up-converted to the desired RF frequency by two
quadrature mixers fed by the LO signals. The signal is then amplified by a driver and power amplifier stage.
MCFG0C_PA_ramp[4..3]
00
01
10
11
T PA (μs)
3
8.5
15
23
Rise/fall (μs)
2.5/2
5/3
10/6
20/10
Table 2
www.RFM.com E-mail: info@rfm.com
? 2009-2010 by RF Monolithics, Inc.
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TRC103 - 11/29/12
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